The present disclosure relates to a semiconductor device and a method for manufacturing the same. More particularly, the present disclosure relates to a semiconductor device including a MISFET (Metal-insulator semiconductor field-effect transistor) having a gate insulating film including a high-k material and a gate electrode including a metal film (hereinafter referred to as a “metal gate electrode”).
There are demands for further miniaturizing CMOS (Complementary metal-oxide semiconductor) devices. Further miniaturization of CMOS devices requires a reduction in the thickness of a gate insulating film. However, a further reduction in the thickness of a conventional gate insulating film which is a silicon oxide film may result in an increase in the leak current, thereby increasing the standby current of an LSI (Large scale integration). Thus, the approach of reducing the thickness of the gate insulating film which is a silicon oxide film has reached its limits. Public attention has been drawn to CMIS (Complementary metal-insulator semiconductor) devices in which an insulating film of a high-k material, instead of a silicon oxide film, is used as the gate insulating film. The electrical thickness of an insulating film made of a high-k material can be made small even if the physical thickness thereof is large, and it is expected with such an insulating film that the thickness of the gate insulating film can be further reduced. The high-k material of a gate insulating film that is currently considered most promising is nitrided hafnium silicate (HfSiON).
Also with the gate electrode, the depletion of a conventional polysilicon electrode has become non-negligible, and metal gate electrodes free from depletion have been researched and developed actively.
On the other hand, properties required of the gate insulating film and the gate electrode are different between N-type MISFETs and P-type MISFETs. Specifically, it is preferred that the effective work function is low in an N-type MISFET and that it is high in a P-type MISFET. Thus, there has been proposed a process for forming N-type MISFETs and P-type MISFETs having gate insulating films and gate electrodes of different properties from each other (see, for example, S. C. Song, et al., “Highly Manufacturable 45 nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration”, VLSI, 2006, p. 16-17).
Referring now to FIGS. 6A to 6D and 7A to 7B, a conventional method for manufacturing a semiconductor device will be described. In the figures, “NTr” on the left denotes an N-type MISFET formation region Ntr where an N-type MISFET is formed, and “PTr” on the right denotes a P-type MISFET formation region PTr where a P-type MISFET is formed.
First, as shown in FIG. 6A, a device isolation region 111 is formed in an upper portion of a semiconductor substrate 110, thereby forming a first active region 110a in the N-type MISFET formation region Ntr of the semiconductor substrate 110 and a second active region 110b in the P-type MISFET formation region PTr thereof. Then, a p-type well region 112a is formed in the N-type MISFET formation region Ntr of the semiconductor substrate 110, and an n-type well region 112b is formed in the P-type MISFET formation region PTr thereof. Then, a first insulating film 113 and a first conductive film 114 are formed in this order across the entire upper surface of the semiconductor substrate 110, and an amorphous silicon film 115 covering a portion of the first conductive film 114 that is formed over the first active region 110a is formed selectively.
Then, as shown in FIG. 6B, a portion of the first insulating film 113 and the first conductive film 114 that is formed over the second active region 110b is removed using the amorphous silicon film 115 as a mask. Then, a second insulating film 116 and a second conductive film 117 are formed in this order on a portion of the upper surface of the semiconductor substrate 110 that is not covered by the first insulating film 113 and on the amorphous silicon film 115, and an amorphous silicon film 118 covering a portion of the second conductive film 117 that is formed over the second active region 110b is formed selectively.
Then, as shown in FIG. 6C, a portion of the second insulating film 116 and the second conductive film 117 that is formed over the first active region 110a is removed using the amorphous silicon film 118 as a mask.
Then, as shown in FIG. 6D, after the amorphous silicon films 115 and 118 are removed, a polysilicon film 120 is formed on the first conductive film 114, on the second conductive film 117, and on a portion of the upper surface of the semiconductor substrate 110 that is not covered by the first insulating film 113 or the second insulating film 116.
Then, as shown in FIG. 7A, the first conductive film 114, the second conductive film 117 and the polysilicon film 120 are removed selectively. As a result, a first gate electrode 200 including the first conductive film 114 and the polysilicon film 120 is formed over the first active region 110a, and a second gate electrode 201 including the second conductive film 117 and the polysilicon film 120 is formed over the second active region 110b. 
Then, as shown in FIG. 7B, the first insulating film 113 and the second insulating film 116 are removed selectively. As a result, the first gate electrode 200 is formed over the first active region 110a, with a first gate insulating film which is the first insulating film 113 interposed therebetween, and the second gate electrode 201 is formed over the second active region 110b, with a second gate insulating film which is the second insulating film 116 interposed therebetween. A conventional semiconductor device can be produced as described above.
Herein, it is possible to optimize the properties of the N-type MISFET and those of the P-type MISFET by using an HfSiON film for the first insulating film 113, a TiN film for the first conductive film 114, an HfO2 film for the second insulating film 116, and a TaN film for the second conductive film 117.